vhdl gripes

Was implementing a FIR today. If you have a FIR obviously you'll have an adder tree. But how does one declare a generic adder tree component? It would be nice to be able to do (pardon the syntax errors):

entity signed_adder_tree is
  generic (N, IN_WIDTH: positive);
  type din_T is array(0 to N-1) of std_logic_vector(IN_WIDTH-1 downto 0);
  port (c: std_logic; din: din_T; dout: std_logic_vector(IN_WIDTH+log2(N)-1 downto 0));
end signed_adder_tree;


but this is unfortunately not possible. So instead, I need to concat the inputs into one humongous vector (since std_logic_vector(N*IN_WIDTH-1 downto 0) is obviously possible) and then manually unwrap inside. Such a waste of time! Fortunately, VHDL-200x has this :)


Another minor gripe I have is the inability to do recursive instantiation of components, i.e. instantiate an entity from its own architecture. Instead, I need to do iteration... which means a need to declare lots of signals... imagine the same adder_tree... if I could write it as (again, with very relaxed syntax, and ignoring the pipelining):

architecture arc of signed_adder_tree is
begin
  base_case: if N = 1 generate
    dout <= din(0);
  end generate;

  recurse: if N > 1 generate
    signal dd: array(0 to (N-1)/2) of std_logic_vector(IN_WIDTH downto 0);
  begin
    l1: for i in 0 to N/2-1 generate
      rr: entity work.addld_pipe
      port map (c=>c, a=>din(2*i), b=>din(2*i+1), s=>dd(i));
    end generate;

    ll: if N mod 2 = 1 generate
      process (c)
      begin
        if rising_edge(c) then
        dd(dd'high) <= signed_resize(din(din'high), IN_WIDTH+1);
        end if;
      end process;
    end generate;

    lr: entity work.adder_tree generic map (dd'length, IN_WIDTH+1)
      port map (c=>c, din=>dd, dout=>dout);
  end generate;
end arc;

How nice would this be!? But instead, now I have to declare all those intermediate signals... yuck...