design choices, more tool gripes

Ooh the past week has just whizzed by hah... and i shall try not to use capital letters anymore...

this wk, 1 of the things i was doing was to implement a phase-shifter (digital). 2 issues:

1. no real math library yet, so needed to get the trig tables in.
2. needed to get some values into the chip to act as rom.

for (1), i just wrote a matlab/octave program to output a vhdl file containing a package containing the trig table (one quadrant of cosine). easy.

for (2), i wrote a smallish extension to emulate a 2d unconstrained array (to move stuff into the INIT_xx, INITP_xx generics of RAMB16_Sxx_Syy). 2 problems:

first, the INIT_xx and INITP_xx stuff... no documentation available from ise 8.1 (which i'm using) as well as ise 10 (the default doc on xilinx's site). the lib doc referred to the constraint doc, and the constraint doc referred to the lib doc. whoopie. instead, had to search for ise 7's documentation, and the description was in the constraint doc. OR, read the VITAL sim source file...

second, my extension included a pair of functions to access the "elements" of the array:
function get_bv_elt(spec: varray_spec_T; b: bit_vector; n: natural) return bit_vector;
function set_bv_elt(spec: varray_spec_T; b: bit_vector; n: natural; v: bit_vector) return bit_vector;

so the second function was meant to be used as: o := set_bv_elt(spec, o, index, new_val), for e.g... this worked ok with modelsim, but synplify bombed out with an "out of memory"... seems like the compiler is memoizing each function call (i have large loops)... how to solve? convert the setter into a procedure, which reduces its reusability... not that it took alot of work, but... why can't the compiler just garbage collect the unneeded stuff?? wasted 15 min of my time (10 min waiting for it to compile 2x).. grrr..